FIR digital filtering of delta modulated signals

The problem of the implementation of an FIR (finite impulse response) filter which has delta modulated (DM) signals of the same step size and bit rate at input and output is considered. Algorithms are proposed for the direct implementation of a DM multiplier with arbitrary constant and a full-adder using piecewise linear approximation. Error analysis is performed for these algorithms, and simple hardware implementations are proposed. The design of DM systems so that the direct arithmetic operations are possible is considered. Finally, FIR filters based on the proposed arithmetic units are designed, and computer simulation results are presented