Reducing the Leakage Current and PDP in the Quasi-Floating Gate Circuits

Recently, by increasing the usage of battery-powered systems such as laptop, mobile, wristwatch and etc. power dissipation is becoming an important constraint in each electronically design. To reduce the power dissipation, it has been offered to use a floating gate MOSFET technology. According to decline the size of the circuits and power dissipation, thickness of the gate oxide will decrease and this causes a big leakage current in the VLSI circuits. So, new methods should be recommended to maintain the charges in the nodes. In this paper we try to present a new Quasi FGMOS technique to solve this problem. Simulations in a 65 nm process show that by using our proposed Quasi FGMOS, there will be lower PDP and also leakage current than conventional Quasi FGMOSs have.