Reducing the Leakage Current and PDP in the Quasi-Floating Gate Circuits

Author

Razaghian, Farhad ; Bonakdarpour, Sahar

Author_Institution

Dept. of Electr. Eng., Islamic Azad Univ., Tehran, Iran

fYear

2012

fDate

27-30 May 2012

Firstpage

1

Lastpage

4

Abstract

Recently, by increasing the usage of battery-powered systems such as laptop, mobile, wristwatch and etc. power dissipation is becoming an important constraint in each electronically design. To reduce the power dissipation, it has been offered to use a floating gate MOSFET technology. According to decline the size of the circuits and power dissipation, thickness of the gate oxide will decrease and this causes a big leakage current in the VLSI circuits. So, new methods should be recommended to maintain the charges in the nodes. In this paper we try to present a new Quasi FGMOS technique to solve this problem. Simulations in a 65 nm process show that by using our proposed Quasi FGMOS, there will be lower PDP and also leakage current than conventional Quasi FGMOSs have.

Keywords

MOSFET; leakage currents; nanoelectronics; floating gate MOSFET technology; gate oxide; leakage current; quasi FGMOS technique; quasi-floating gate circuit; size 65 nm; Integrated circuit modeling; Inverters; Leakage current; Logic gates; Power dissipation; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Technology (S-CET), 2012 Spring Congress on

Conference_Location

Xian

Print_ISBN

978-1-4577-1965-3

Type

conf

DOI

10.1109/SCET.2012.6342135

Filename

6342135