DocumentCode :
1992774
Title :
Performance tradeoffs in sequencer design on a new G4 PowerPCTM microprocessor
Author :
Rupley, Jeff, II ; Holloway, David
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
fYear :
2000
fDate :
2000
Firstpage :
88
Lastpage :
94
Abstract :
The microprocessor discussed in this paper is a new member of the G4 family of PowerPC microprocessors with AltiVecTM enhanced technology, intended for high performance desktop systems. This four-way superscalar design is more deeply pipelined than previous designs in order to achieve greater frequency. The challenge in increasing frequency is to translate most or all of that increase into performance increases, and this requires careful analysis from a performance simulator. This paper specifically looks at how the interaction between frequency and performance goals affected the design of the new G4 instruction sequencer
Keywords :
microcomputers; microprocessor chips; performance evaluation; pipeline processing; virtual machines; AltiVec enhanced technology; G4 PowerPC microprocessor; G4 instruction sequencer design; four-way superscalar design; high performance desktop systems; performance simulator; performance tradeoffs; pipelining; Costs; Engines; Frequency; Graphics; Logic; Microarchitecture; Microprocessors; Pipelines; Power generation; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Analysis of Systems and Software, 2000. ISPASS. 2000 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-6418-X
Type :
conf
DOI :
10.1109/ISPASS.2000.842286
Filename :
842286
Link To Document :
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