DocumentCode
1993539
Title
A 12 Gb/s chip-to-chip AC coupled transceiver
Author
Wang, Yu-Shun ; Hsieh, Min-Han ; Wu, Yi-Chi ; Liu, Chia-Ming ; Chiu, Hsien-Chen ; Lin, Bing-Feng ; Chen, Charlie Chung-Ping
Author_Institution
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2011
fDate
15-18 May 2011
Firstpage
1692
Lastpage
1695
Abstract
A differential AC coupled transceiver for high-speed and low-swing has been implemented in a 0.18μm CMOS process. The proposed architecture includes a pulse receiver and a broadband limiting amplifier to recover a NRZ signal from a 75fF capacitive coupled channel. The system works at 12Gb/s through 10cm FR4 printed circuit board interconnect, while dissipating only 13.5mW with a bit error rate less than 10-12.
Keywords
limiters; printed circuits; radio transceivers; wireless channels; CMOS process; FR4 printed circuit board; NRZ signal; bit rate 12 Gbit/s; broadband limiting amplifier; capacitance 75 fF; capacitive coupled channel; differential AC coupled transceiver; pulse receiver; size 0.18 mum; size 10 cm; Bandwidth; CMOS integrated circuits; CMOS technology; Driver circuits; Limiting; Receivers; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location
Rio de Janeiro
ISSN
0271-4302
Print_ISBN
978-1-4244-9473-6
Electronic_ISBN
0271-4302
Type
conf
DOI
10.1109/ISCAS.2011.5937907
Filename
5937907
Link To Document