A fully-adjustable dynamic range capacitance sensing circuit in a 0.15µm 3D SOI process

We describe a fully-adjustable dynamic range capacitance sensor circuit implemented with switched capacitors in a 3D process. The dynamic range and sampling frequency are set by the frequency of two clock inputs that control an on-chip four phase non-overlapping clock generation circuit. The chip also contains a bandgap reference, increasing the accuracy of the capacitance measurements. It also has full temperature control capabilities via the PTAT circuit and resistive heating element. The circuits were fully simulated using the Cadence IC 6 simulation tool. The 3D chips were provided by Lincoln Lab at Massachusetts Institute of Technology (MITLL). MITLL fabricate a 3D wafer by bonding 3 stacked wafers each from the IBM silicon over insulator (SOI) 0.15 μm process.