A study of the robustness against SEUs of digital circuits implemented with FPGA DSPs

Author

Serrano, Felipe ; Clemente, J.A. ; Mecha, Hortensia

Author_Institution

Comput. Archit. Dept., Univ. Complutense de Madrid (UCM), Madrid, Spain

fYear

2013

fDate

23-27 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in Xilinx^TMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

Keywords

digital signal processing chips; field programmable gate arrays; integrated circuit reliability; radiation hardening (electronics); FPGA DSPs; SEU effect; Xilinx FPGA; digital circuits; digital signal processors; fault-injection platform; probability of occurrence; reliability; Circuit faults; Digital circuits; Digital signal processing; Emulation; Field programmable gate arrays; Robustness; Single event upsets;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2013 14th European Conference on

Conference_Location

Oxford

Type

conf

DOI

10.1109/RADECS.2013.6937459

Filename

6937459