Title :
Buffer memory requirements in DSP applications
Author :
Adé, Marleen ; Lauwereins, Rudy ; Peperstraete, J.A.
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
Abstract :
Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyse a graph´s consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical
Keywords :
buffer storage; concurrency control; parallel processing; programming environments; signal processing; software prototyping; DSP applications; FPGA; GRAPE-II; buffer memory requirements; deadlock-free static schedule; emulation hardware; graph consistency; minimal required buffer sizes; parallel paths; rapid prototyping environment; single paths; synchronous multi-rate data flow graphs; Data flow computing; Digital signal processing; Field programmable gate arrays; Flow graphs; Hardware; Optimal scheduling; Pipelines; Prototypes; Scheduling algorithm; System recovery;
Conference_Titel :
Rapid System Prototyping, 1994. Shortening the Path from Specification to Prototype. Proceedings., Fifth International Workshop on
Conference_Location :
Grenoble
Print_ISBN :
0-8186-5885-1
DOI :
10.1109/IWRSP.1994.315904
