An FPGA Router for Alternative Reconfiguration Flows

An FPGA router is developed using both the PathFinder and A* algorithms. Instead of the popular routing channel and rack model that is widely adopted by the research community, a modified routing model based on the architecture description for Xilinx devices (XDLRC) is applied. As a result, the proposed router works for any real device with an XDLRC description, which makes it a good candidate for FPGA reconfiguration flows. Tests of routing MCNC benchmark circuits are run for five different FPGA devices. The performance results are comparable to those of VPR and ROCR. Two useful application of the proposed router are demonstrated. One is fast module assembly, which runs tens of times faster than the vendor tool. The other is routing-free sandbox creation which outperforms OpenPR in terms of run time.