Title :
−99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver
Author :
Shi, Congyin ; Wang, Chuan ; Ye, Le ; Liao, Huailin
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
In this paper, a low in-band phase noise integer-N CMOS frequency synthesizer is proposed for global navigation satellite system (GNSS) receiver. The synthesizer adopts dual-loop architecture, which consists of a double-balanced mixer and two full PLL loops, to reduce the divide ratio so as to lower the in-band phase noise. It achieves 1MHz resolution and -99 dBc/Hz@10kHz with fixed reference clock of 10MHz, which is compatible to commercial atomic frequency sources. Moreover, a novel adaptive frequency calibration policy is implemented to avoid mis-locking at the unwanted mirror frequency. The PLL is fabricated in 0.18-μm CMOS technology, covers most GPS, Galileo and Beidou-II bands and was integrated in a GNSS receiver with 46MHz intermediate frequency (IF).
Keywords :
CMOS integrated circuits; calibration; frequency synthesizers; phase locked loops; radio receivers; satellite navigation; Beidou-II bands; CMOS technology; GNSS receiver; GPS; Global Navigation Satellite system receiver; PLL loops; adaptive frequency calibration policy; antimislocking frequency calibration; commercial atomic frequency sources; double-balanced mixer; dual-loop integer-N PLL; frequency 1 MHz; frequency 10 MHz; frequency 10 kHz; frequency 46 MHz; in-band phase noise; in-band phase noise integer-N CMOS frequency synthesizer; size 0.18 mum; Frequency control; Frequency synthesizers; Global Positioning System; Mixers; Phase locked loops; Phase noise; Synthesizers;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937953