A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3 nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline n/sup +/ poly gate. It is found that the PVD TiN has higher metal-to-SiO/sub 2/ barrier height (/spl sim/3.77 eV) than that of the CVD TiN (3.62 eV). The CVD W/PVD TiN gates without high temperature (>900 C) RTP anneal show good electrical characteristics on 3 nm gate oxide, and the CVD TiN is less favorable due to its high impurities. High temperature anneal cause fluorine in CVD W to diffuse and interact with the gate oxide which adversely affect the gate oxide integrity (GOI). The remote plasma nitrided gate oxide (RPNO) provides a barrier between the TiN and gate oxide, and thus prevents or reduces the F-SiO/sub 2/ interaction, resulting in metal gate GOI comparable to that of poly gate. The CVD metal gate is a good candidate for the non-conventional, high aspect ratio grooved gate structures due to its good conformality.