A flexible hardware implementation of SHA-1 and SHA-2 Hash Functions

This paper summarizes the design of a reprogrammable Application Specific Integrated Circuit capable of performing all members of the Secure Hash Algorithm (SHA) group of Hash Functions. The need for high-speed cryptography is introduced, as well as the SHA-1 and SHA-2 Hash Functions and their operation. Work performed at other institutions to improve throughput and power consumption is presented with advantages and disadvantages discussed. The ASIC design is then discussed, with comparisons made to previously published ASIC and FPGA implementations. The possibility of using this ASIC architecture for the SHA-3 candidates, as well as the Message Digest (MD) families of Hash Functions is suggested as an area of future work as it is shown the ASIC Architecture designed would be capable of this with only program modifications required.