Title :
Design of radar co-controller based on FPGA
Author :
Shao, Zhidong ; Lu, Aiyu ; Chai, Minggang
Author_Institution :
Sch. of Meas. & Opt. Eng., Nanchang Hangkong Univ., Nanchang, China
Abstract :
The work cycle of modern radar is shorter and shorter, furthermore, the volume of data that need to be processed becomes larger and larger in a period. It is very difficult for the computer to real-time process large amounts of data and to real-time control radar. This paper proposes designing an FPGA-based co-controller between the computer and radar subsystems, in order to realize the real-time control of the radar. This paper introduces the overall design of the radar co-controller based on FPGA. It comes up with the designs of data buffer memory module, DSP link interface module, radar sub-unit control module and waveform generator control module in VHDL language on QuartusII. The experimental results show that each module of the radar co-controller can meet the requirements, and can correctly process data and command. Design of FPGA-based can obtain application specific radar co-controller chip, and has independent intellectual property rights.
Keywords :
field programmable gate arrays; hardware description languages; radar applications; real-time systems; DSP link interface module; FPGA; QuartusII; VHDL language; data buffer memory module; intellectual property rights; radar cocontroller design; radar subunit control module; real-time control; waveform generator control module; Arrays; Digital signal processing; Educational institutions; Field programmable gate arrays; Laser radar; Real time systems; FPGA; VHDL; radar co-controller; real-time control;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location :
Yichang
Print_ISBN :
978-1-4244-8162-0
DOI :
10.1109/ICECENG.2011.6058065