Title :
IDVP (Intra-Die Variation Probe) for System-On-Chip (SoC) Infant Mortality screen
Author :
Latif, Mohd Azman Abdul ; Ali, Noohul Basheer Zain ; Hussin, Fawnizu Azmadi
Author_Institution :
SoC Quality & Reliability, Intel Corp., Bayan Lepas, Malaysia
Abstract :
Abstract-Used materials, oxides thicknesses, and ultra-small channel lengths are contributors to the impact of well known reliability issue such as NBTI (Negative Bias Temperature Instability). This paper describes a case study using an Intra-Die Variation Probe (IDVP) test to screen out Infant Mortality (IM) failures. The approach is pursued by applying the learning of yield and reliability on 45 nm process technology for the System-On-A-Chip (SoC) products. Using this approach, the IDVP test is determined as a better reliability screen than the Electrical Test (E-Test), due to poor E-Test coverage in the Gross Failure Area (GFA). It has been revealed that the GFA only becomes visible after Burn In stress and we found that the IM failures are a mixture of post-stress Automated Test Equipment (ATE) failures. This approach will produce an outgoing level of quality that enables the 45 nm SoC products to reduce burn-in sampling in the production flow and will be proliferated to the 32 nm process technology products.
Keywords :
system-on-chip; automated test equipment failures; burn-in sampling; e-test coverage; electrical test; gross failure area; infant mortality failures; intra-die variation probe test; negative bias temperature instability; oxides thickness; process technology products; production flow; reliability screen; system-on-chip infant mortality screen; ultra-small channel lengths; used materials; Clocks; Logic gates; Materials; Oscillators; Reliability; Stress; System-on-a-chip; IDVP; Infant Mortality; NBTI; Process Variation;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5938001