A low-leakage parallel CRC generator for ultra-low power applications

Author

Alarcón, Louis P. ; Liu, Tsung-Te ; Rabaey, Jan M.

Author_Institution

Berkeley Wireless Res. Center, Univ. of California, Berkeley, Berkeley, CA, USA

fYear

2011

fDate

15-18 May 2011

Firstpage

2063

Lastpage

2066

Abstract

Unlike static CMOS circuits, the standby energy in sense amplifier-based pass transistor logic (SAPTL) circuits can be decoupled from its performance, allowing separate optimization strategies for leakage and speed. In this paper, a 64-byte parallel cyclic-redundancy check (CRC) generator is designed and implemented using asynchronous 90nm SAPTL circuits, with a simulated minimum energy point that is 25% lower than the equivalent complementary static CMOS implementation. The low leakage operation results in (a) an 7.9X reduction in measured energy when V_DD is reduced from 1V to 0.3V at α = 0.1 and (b) a 10% reduction in measured delay with a stack forward body bias of 0.4V, with no corresponding increase in energy.

Keywords

asynchronous circuits; circuit optimisation; logic design; low-power electronics; 64-byte parallel cyclic-redundancy check generator; asynchronous SAPTL circuits; complementary static CMOS implementation; low-leakage parallel CRC generator; optimization strategies; sense amplifier-based pass transistor logic circuits; size 90 nm; ultralow-power applications; voltage 0.4 V; voltage 1 V to 0.3 V; CMOS integrated circuits; Delay; Driver circuits; Energy measurement; Generators; Logic gates; Transistors; 90nm; CRC; SAPTL; asynchronous; low energy; low leakage; pass transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5938003

Filename

5938003