A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles

Recently DPA resistant logic styles are of great concern. As far as we know, each kind of logic style has its own drawbacks. Masking logic styles can easily be attacked by the template attack. For dual-rail logic styles, TDPL can only keep the total power consumption of the whole cycle constant; as for WDDL, it becomes more and more difficult to efficiently match the interconnect capacitances of differential wires with shrinking feature sizes. To avoid these drawbacks, we present a new direction for routing effort to solve the unbalanced interconnection problem. By using three-phase logic and removing the load dependent power consumption in the evaluation phase and discharge phase, our logic style is insensitive to the unbalanced interconnect capacitances of differential wires. Additionally, the early propagation effect is another threat to certain DPA resistant logic styles. We also propose a theoretical method to solve it at the system level.