A very efficient single-iteration oldest-out data sorter

This work introduces a new hardware implementation for oldest-out sorters. The circuit operates serially and reorders the data in a single clock cycle, eliminating the oldest value when a new input enters the system. The use of a simple standard cell without global ripple-type signals results in a completely modular implementation which is little affected by the system size. Tests were performed in three FPGAs from the Virtex families, which are employed in other works described in the literature; the proposed approach requires 25% less resources (LUTs) and is about 40% faster than the best implementation reported so far.