Title :
Power gating scheduling for power/ground noise reduction
Author :
Hailin Jiang ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA
Abstract :
Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh. In this paper, we propose a GA-based approach to schedule power gating considering power/ground noise. We introduce a simulation-based method to accurately and efficiently estimate the worst case noise, taking all the current sources, inductance and decaps´ effects into consideration. We also present an incremental scheduling procedure considering the dynamic changes of decap configuration. Experimental results show that by optimally scheduling the wake-up order under time constraints, our technique can reduce noise up to 50% compared to waking gated blocks simultaneously. The quality of results depends upon the total wake-up time constraint, locations of gated blocks, current densities of gated blocks, and decap distribution.
Keywords :
current density; genetic algorithms; integrated circuit noise; leakage currents; power grids; power supply circuits; GA approach; current densities; decap configuration; decap distribution; gated blocks; genetic algorithms; leakage power; power gating scheduling; power grid; power/ground noise reduction; simulation-based method; wake-up order; wake-up time constraint; Circuits; Clocks; Delay; Noise reduction; Permission; Power grids; Power supplies; Sleep; Time factors; Transistors; Power gating; power supply noise; scheduling;
Conference_Titel :
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-60558-115-6