DocumentCode
1996837
Title
Fault tolerant computing for stream DSP applications using GALS multi-core processors
Author
Yu, Zhiyi ; Shi, Zewen ; Zeng, Xiaoyang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2011
fDate
15-18 May 2011
Firstpage
2305
Lastpage
2308
Abstract
This paper presents a multi-core processor with globally asynchronous locally synchronous (GALS) clocking style designed to achieve soft error tolerance for stream DSP applications, and to maintain system throughput energy efficiently. Each processor in the chip can be combined with one of its neighbor processors to run the same programs and their results are equivalence checked to detect the soft error occurrence. When error occurs in some processor, the program in that processor (not the whole chip) is re-executed from the saved state to recover from the error. Due to the programming model of stream DSP applications, each processor can be isolated by FIFOs in the proposed multi-core processors, and fault detection and recovery can be done with low overhead. Furthermore, the GALS clocking style allows adjusting the frequency of the processors hit by a soft error-not the frequency of the whole chip-to maintain the system throughput, which results high energy efficiency.
Keywords
digital signal processing chips; fault tolerant computing; multiprocessing systems; FIFO; GALS multicore processors; fault tolerant computing; soft error tolerance; stream DSP applications; Clocks; Digital signal processing; Fault detection; Fault tolerance; Fault tolerant systems; Multicore processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location
Rio de Janeiro
ISSN
0271-4302
Print_ISBN
978-1-4244-9473-6
Electronic_ISBN
0271-4302
Type
conf
DOI
10.1109/ISCAS.2011.5938063
Filename
5938063
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