Title :
Efficient implementation of Advanced Encryption Standard (AES) for ARM based platforms
Author :
Kumar, Mohit ; Singhal, Apoorva
Author_Institution :
Univ. Sch. of Inf. Technol., Guru Gobind Singh Indraprastha Univ., New Delhi, India
Abstract :
Now a days, hi-tech secure products need more services and more security. Furthermore, the corresponding market is now oriented towards more flexibility. In this paper, we have implemented Advanced Encryption Algorithm for ARM based platforms. The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael algorithm as its winner. AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits, whereas Rijndael can be specified with key and block sizes in any multiple of 32 bits, with a minimum of 128 bits and a maximum of 256 bits. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel Strong ARM SA-1110 Microprocessor.
Keywords :
cryptography; embedded systems; instruction sets; microprocessor chips; AES; ARM based platform; ARM core; ARM instruction set architecture; Intel strong ARM SA-1110 microprocessor; Rijndael algorithm; U.S. National Institute of Standards and Technology; advanced encryption algorithm; advanced encryption standard; architectural parameter; block size; embedded industry; hi-tech secure product; linear mixing layer; optimum performance; performance improvement; Algorithm design and analysis; Computer architecture; Educational institutions; Encryption; NIST; Program processors; Registers; AES; ARM microprocessor; cache memories; code optimization;
Conference_Titel :
Recent Advances in Information Technology (RAIT), 2012 1st International Conference on
Conference_Location :
Dhanbad
Print_ISBN :
978-1-4577-0694-3
DOI :
10.1109/RAIT.2012.6194473