Logic, fault, and design error simulation based on an integrated hardware array

Simulation is essential for the design and verification of digital systems and simulation tools are widely used to analyze the behavior of digital circuits. This paper describes an integrated hardware array specialized for digital logic, fault, and design error simulation. Hardware simulation, using a high performance special purpose architecture such as the integrated hardware array, is still a viable approach for large and complicated circuits. In order to reduce the cost and to achieve high performance, the integrated hardware array adopts a direct mapping parallelism which directly maps the circuit topology onto the hardware array. Experimental results are given