• DocumentCode
    1997766
  • Title

    A New Methodology for Studying Realistic Processors in Computer Science Degrees

  • Author

    Gomez Requena, Crispin ; Gomez, Maria Eugenia ; Sahuquillo, Julio

  • Author_Institution
    Dept. de Sist. Informdticos, Univ. de Castilla-La Mancha, Albacete, Spain
  • fYear
    2013
  • fDate
    20-24 May 2013
  • Firstpage
    1283
  • Lastpage
    1290
  • Abstract
    The architecture of current microprocessors has suffered a vertiginous evolution in the last years, leading to the development of multithreaded multicore processors. The inherent complexity makes teaching students how current processors work a complex task and this has led most universities to study superscalar or multithreaded processors in a very simplified manner. This situation aggravates even more at lab sessions. Due to this fact students have a faraway view from real working of current multicore processors. To deal with this hard shortcoming, we designed a new methodology to approach students to real processor hardware, that has been successfully used at the Universitat Politècnica de València. The methodology is based on the use of a very detailed and accurate simulator that provides support to simulate all the main components of current microprocessors. Due to the simulator complexity, it is introduced through several phases in a progressive manner, which leads the students to achieve a solid learning about how current processors work, even including the a detailed model for the on-chip network that connects the cores of the system. Results demonstrate that students are able to use the simulator in a reasonable time period, and understand at the same time the more complex concepts of commercial processors. Furthermore some of them have been able to developed projects with the studied simulation framework that have been published in top international research conferences, such as PACT and IPDPS.
  • Keywords
    learning (artificial intelligence); multi-threading; multiprocessing systems; IPDPS; PACT; computer science degrees; multithreaded multicore processors; on-chip network; real processor hardware; simulator complexity; solid learning; top international research conferences; Cache memory; Computer science; Multicore processing; Multiprocessor interconnection; Pipelines; Program processors; Computer architecture; Multicore processors; Teaching; simulators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    978-0-7695-4979-8
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2013.13
  • Filename
    6651018