An HDL-synthesized gated-edge-injection PLL with a current output DAC

Author

Dongsheng Yang ; Wei Deng ; Ueno, Tomohiro ; Siriburanon, Teerachot ; Kondo, Satoshi ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2015

fDate

19-22 Jan. 2015

Firstpage

2

Lastpage

3

Abstract

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm². It achieves the best performance-area trade-off.

Keywords

CMOS digital integrated circuits; clocks; digital-analogue conversion; low-power electronics; phase locked loops; voltage-controlled oscillators; HDL-synthesized gated-edge-injection PLL; current output DAC; digital CMOS process; digital-to-analog converter; edge injection; frequency 0.9 GHz; fully synthesizable PLL; interpolative-phase coupled oscillator; low power PLL; on-chip clock generation; phase-locked loops; power 0.78 mW; size 65 nm; small area PLL; Clocks; Jitter; Logic gates; Oscillators; Phase locked loops; Standards; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

978-1-4799-7790-1

Type

conf

DOI

10.1109/ASPDAC.2015.7058917

Filename

7058917