DocumentCode
1997858
Title
Self-Programmable Shared BIST for Testing Multiple Memories
Author
Bahl, Swapnil ; Srivastava, Vishal
Author_Institution
STMicroelectronics Pvt Ltd., Noida
fYear
2008
fDate
25-29 May 2008
Firstpage
91
Lastpage
96
Abstract
Hundreds of memory instances and their frequency of operation have ruled out the possibility of sharing test structures amongst the embedded memories. This paper discusses the techniques and flow for sharing an embedded memory BIST for the at- speed testing of multiple memories on a typical SoC.
Keywords
built-in self test; embedded systems; logic testing; semiconductor storage; system-on-chip; SoC; at- speed testing; built-in-self test; embedded memories; multiple memory testing; pipeline architecture; self-programmable shared BIST; semiconductor memory; Automatic testing; Built-in self-test; Costs; Engines; Fabrication; Frequency; Logic arrays; Random access memory; System testing; Time to market; Built-in Self-test (BIST); Memory testing and Semiconductor memory.; Pipeline architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2008 13th European
Conference_Location
Verbania
Print_ISBN
978-0-7695-3150-2
Type
conf
DOI
10.1109/ETS.2008.16
Filename
4556033
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