RSA encryption system using encoded multiplier and vedic mathematics

This paper presents an efficient design and implementation of RSA Encryption System using Encoded Multiplier. RSA algorithm is implemented based on ancient Indian Vedic Mathematics. The speed of the system mainly depends on multipliers and adders. To reduce the speed the multiplier architecture is modified using a new encoded algorithm. Number of partial products in this architecture is reduced to half and thus speeds up the operation. In this algorithm no multipliers are required for multiplication process and the number of adders required is also reduced. The most significant aspect of this paper is the development of encoded architecture and embedding it in RSA circuitry. The coding is done in Verilog HDL and FPGA implementation using Xilinx Spartan library.