Title :
Highly parallel fractional motion estimation engine for Super Hi-Vision 4k×4k@60fps
Author :
Huang, Yiqing ; Liu, Qin ; Ikenaga, Takeshi
Author_Institution :
Syst. LSI Lab., Waseda Univ., Kitakyushu, Japan
Abstract :
One Super Hi-Vision (SHV) 4k times 4k @60 fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost, 48% clock cycle is saved based on our mode pre-filtering scheme. By further check the motion cost of neighboring search points, our directional one-pass scheme can achieve reduction of 50% clock cycle and 36% hardware cost. Secondly, in the hardware level, two parallel improved schemes namely 16-Pel interpolation and MB-parallel processing are given out. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 80.68% pixels are reused and the related memory access is saved. Furthermore, one parity pixel organization scheme is proposed to solve memory access conflict of MB-parallel processing. By using TSMC 0.18 mum technology in worst work conditions (1.62 V, 125degC), our FME engine can achieve real-time processing for SHV 4ktimes4k@60fps with 976.5 k gates hardware.
Keywords :
filtering theory; motion estimation; parallel processing; 16-Pel interpolation; MB-parallel processing; complexity reduction schemes; directional one-pass scheme; highly parallel fractional motion estimation; neighboring search points; one parity pixel organization scheme; prefiltering scheme; size 0.18 mum; super hi-vision; unified pixel block loading scheme; Automatic voltage control; Clocks; Costs; Engines; Frequency; Hardware; Large scale integration; Motion estimation; Throughput; Video compression;
Conference_Titel :
Multimedia Signal Processing, 2009. MMSP '09. IEEE International Workshop on
Conference_Location :
Rio De Janeiro
Print_ISBN :
978-1-4244-4463-2
Electronic_ISBN :
978-1-4244-4464-9
DOI :
10.1109/MMSP.2009.5293323