Title :
Bus-Based and NoC Infrastructure Performance Emulation and Comparison
Author :
Wang, Ling ; Hao, Jianye ; Wang, Feixuan
Author_Institution :
Sch. of Comput. Sci. & Technol., Harbin Inst. of Technol., Harbin
Abstract :
In this paper, we study and compare the performance of bus-based and mesh-based with spidernet NoC-based infrastructure in Alterapsilas FPGA. We first analysis the inner latency performance of the NoC infrastructure among routers, and we provide two modes to emulate the specific application on those infrastructures for the purpose of performance comparison. It is shown that NoC-based infrastructure performs better than bus-based one in terms of latency when the number of flits contained in the packets exceeds certain threshold. In addition, spidernet-based infrastructure outperforms mesh-based one under the same condition, which verifies the correctness of the theoretical performance analysis.
Keywords :
field programmable gate arrays; network routing; network-on-chip; FPGA; NoC infrastructure performance emulation; bus-based infrastructure; field programmable gate array; inner latency performance; network routing; spidernet-based infrastructure; Costs; Delay; Emulation; Field programmable gate arrays; Information technology; Integrated circuit technology; Network-on-a-chip; Performance analysis; Topology; Very large scale integration; FPGA; NoC; Spidernet;
Conference_Titel :
Information Technology: New Generations, 2009. ITNG '09. Sixth International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-3770-2
Electronic_ISBN :
978-0-7695-3596-8
DOI :
10.1109/ITNG.2009.186
