• DocumentCode
    1998295
  • Title

    A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

  • Author

    Kanemoto, Daisuke ; Oshiro, Keigo ; Yoshida, Keiji ; Kanaya, Haruichi

  • Author_Institution
    Dept. Eng., Univ. of Yamanashi, Kofu, Japan
  • fYear
    2015
  • fDate
    19-22 Jan. 2015
  • Firstpage
    34
  • Lastpage
    35
  • Abstract
    This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.
  • Keywords
    Bluetooth; CMOS digital integrated circuits; digital-analogue conversion; low-power electronics; Bluetooth applications; CMOS process; capacitive digital-to-analog converter; low power dissipation; output buffers; power 350 muW; size 0.18 mum; tri-level capacitive-DAC; word length 10 bit; Arrays; Bluetooth; Capacitors; Educational institutions; Power dissipation; Semiconductor device measurement; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    978-1-4799-7790-1
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2015.7058973
  • Filename
    7058973
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1998295