Stress-aware P/G TSV planning in 3D-ICs

Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated-Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of P/G TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates. Thus, it is necessary to consider the combined effect on delay variation during the P/G TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined P/G TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the P/G TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches.