Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues

Resistive RAM (ReRAM) cross-point memory technology is one of the most promising candidates for future memory designs as it offers small cell area, fast write latency, and excellent scalability. However, it also suffers from more severe reliability issues than other Non-volatile Memory (NVM) technologies. Due to the lack of access device, ReRAM cells cannot be turned off completely and thus write disturbance problem and hard errors can affect the memory array reliability. Moreover, ReRAM cell suffers from temporal variation caused by its stochastic nature, which results in the resistance change. In this paper, pseudo-hard error caused by temporal variation is defined for the first time as a unique type of error in ReRAM cross-point structure. A comprehensive model is proposed to numerically evaluate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard errors. Detailed analysis are presented, and mitigation solutions including dual-port write and test-and-flip strategy are proposed to shed light on reliable ReRAM cross-point memory design.