A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore´s law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.