Two-phase protocol converters for 3D asynchronous 1-of-n data links

Design of fully synchronous System on Chip is becoming a challenging task. This task is even more difficult in advanced nodes and 3D designs, where the local and global variability can turns the timing closure an overwhelming task. In this way, the use of asynchronous circuits for long link and 3D link communication can provide better robustness to both local and inter-die variability and achieve faster timing closure by extending the Globally Asynchronous Locally Synchronous style to 3D architectures. However, while the four-phase protocol is well adapted for on chip Delay Insensitive communication, it cannot be adapted for off chip and 3D interface communication due to potential large interface delays. In this paper, we propose the use of two-phase Delay Insensitive Transition Signaling for 1-of-n codes as well as new four ↔ two-phase data converters. The proposed circuitry is able to reduce 20% the dynamic power and improve two times the four-phase throughput for long link communications.