A high rate digital processing board for the D0 Upgrade

We report on the digital front end board for the D0 Upgrade tracking trigger. Each board receives discriminated signals from 1/40th of the fiber tracker detector scintillating fiber channels over 10 low voltage differential signal, 1 vds, links each capable of 186 Mbytes per second. This data is shared between two daughter cards containing FPLD chips where eight layer tracks, and single layer preshower clusters are found. On the mother board the tracks and clusters are matched to produce a list for a level 1 trigger of tracks, electrons and photons, in Pt ranges and with isolation information. The board also contains FIFO´s which hold 32 crossings (224 clock cycles). The FIFO´s are read out to a level 2 trigger when a level 1 accept is received