Memory conflict analysis for a multi-standard, reconfigurable turbo decoder

This paper presents an efficient architecture to handle memory conflicts of a unified turbo decoder which supports multiple standards like HSPA+, 3GPP-LTE, WiMAX, 3GPP2-CDMA2000 and CCSDS. A unified radix-4 turbo decoder is used as the reconflgurable unit which provides double throughput for some standards. A complete memory conflict analysis for different interleaver patterns has been performed and shows the effect of using radix-4 decoding on the memory conflicts for different standards. Such a conflict adds latency and reduces the throughput significantly. A simple controller is designed to manage the conflicts on the fly. The proposed design has a maximum throughput of 283.104 Mbps.