Design and implementation of two variable multiplier using KCM and Vedic Mathematics

In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier´s architecture is similar to that of a Constant Co-efficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava Multiplier for both 8 bit and 16 bit cases and the results are presented. The proposed multiplier is 1.5 times faster than the other multipliers for 16×16 case and consumes only 76% area for 8×8 multiplier and 42% area for 16×16 multiplier.