• DocumentCode
    1999185
  • Title

    Multiple Independent Gate FETs: How many gates do we need?

  • Author

    Amaru, Luca ; Hills, Gage ; Gaillardon, Pierre-Emmanuel ; Mitra, Subhasish ; De Micheli, Giovanni

  • Author_Institution
    Integrated Syst. Lab., EPFL, Lausanne, Switzerland
  • fYear
    2015
  • fDate
    19-22 Jan. 2015
  • Firstpage
    243
  • Lastpage
    248
  • Abstract
    Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Researchers face then the question: How many gates do we need? In this paper, we address the logic side of this question. We determine whether or not an increasing number of gates leads to more compact logic implementations. For this purpose, we develop a logic synthesis flow that intrinsically exploits a MIGFET switching function. Using simplified design assumptions and device/interconnect models, we synthesize MCNC benchmarks on 5 promising MIGFET devices, with number of gates ranging from 1 to 7. Experimental results evidence nontrivial area/delay/energy minima, located between 1 and 4 gates, depending on a MIGFET switching function and device/interconnect technology.
  • Keywords
    field effect transistors; logic design; logic gates; FET technology; MCNC benchmarks; MIGFET; complex logic circuits; device-interconnect technology; enhanced conduction properties; intelligent switching functions; logic synthesis flow; multiple independent gate field effect transistors; side implementation cost; supplementary gates; Data structures; Delays; Field effect transistors; Frequency modulation; Integrated circuit interconnections; Logic gates; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    978-1-4799-7790-1
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2015.7059012
  • Filename
    7059012