• DocumentCode
    1999283
  • Title

    A GaAs power FET with zero-temperature-coefficient

  • Author

    Tanaka, T. ; Furukawa, H. ; Ueda, D.

  • Author_Institution
    Electron. Res. Lab., Matsushita Electron. Corp., Osaka, Japan
  • fYear
    1997
  • fDate
    10-10 Dec. 1997
  • Firstpage
    557
  • Lastpage
    560
  • Abstract
    A GaAs power FET with zero-temperature-coefficient has been developed for the first time. We found drain current (Id) and threshold voltage (Vth) shifts are strongly dependent on the mechanical stress inside a chip which generates piezoelectric charges in the channel. Such stress is originally caused by the difference of the thermal expansion coefficients of GaAs and base-metal. The sign of piezoelectric charge distribution can be controlled by the tensor product of the stress and crystal orientation. Using this inherent feature of GaAs material, we have developed a new temperature compensation technique of GaAs power FET just by choosing a proper gate orientation.
  • Keywords
    III-V semiconductors; compensation; gallium arsenide; internal stresses; piezoelectricity; power field effect transistors; thermal expansion; GaAs; GaAs power FET; channel piezoelectric charges; crystal orientation; drain current shift; gate orientation; mechanical stress; piezoelectric charge distribution; temperature compensation technique; tensor product; thermal expansion coefficients; threshold voltage shift; zero-temperature-coefficient; FETs; Fabrication; Gallium arsenide; Laboratories; Stress control; Temperature; Tensile stress; Thermal expansion; Thermal resistance; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-4100-7
  • Type

    conf

  • DOI
    10.1109/IEDM.1997.650447
  • Filename
    650447