DocumentCode
1999331
Title
High Throughput Parallel Implementation of Aho-Corasick Algorithm on a GPU
Author
Nhat-Phuong Tran ; Myungho Lee ; Sugwon Hong ; Jaeyoung Choi
Author_Institution
Dept. of Comput. Sci. & Eng., Myongji Univ., Yongin, South Korea
fYear
2013
fDate
20-24 May 2013
Firstpage
1807
Lastpage
1816
Abstract
Pattern matching is an important operation in various applications such as computer and network security, bioinformatics, image processing, among many others. Aho-Corasick (AC) algorithm is a multiple patterns matching algorithm commonly used for such applications. In order to meet the highly demanding performance requirements imposed on these applications, achieving high performance for AC algorithm is crucial. In this paper, we present a high performance parallel implementation of AC algorithm on a Graphic Processing Unit (GPU) which efficiently utilizes the high degree of on-chip parallelism and the memory hierarchy of the GPU so that the aggregate performance (or throughput) of the GPU can be maximized. For this purpose our approach carefully places and caches the input text data and the reference pattern data used for pattern matching in the on-chip shared memories and the texture caches of the GPU. Furthermore, it efficiently schedules the off-chip global memory loads and the shared memory stores in order to minimize the overheads in loading the input data to the shared memories and also to minimize the shared memory bank conflicts. The proposed approach leads to a significant cut-down of the effective memory access latencies and leads to impressive performance improvements. Experimental results on Nvidia GeForce GTX 285 GPU show that our approach delivers up to 127Gbps throughput performance and up to 222-times speedup compared with a serial version running on 2.2Ghz Core2Duo Intel processor.
Keywords
graphics processing units; parallel processing; pattern matching; AC algorithm; Aho-Corasick algorithm; Nvidia GeForce GTX 285 GPU; graphic processing unit; high throughput parallel implementation; memory access latencies; memory hierarchy; off-chip global memory loads; on-chip parallelism; patterns matching algorithm; AC machines; Algorithm design and analysis; Doped fiber amplifiers; Graphics processing units; Instruction sets; Memory management; Pattern matching; Aho-Corasick algorithm; GPU; parallelization; shared-memory bank conflict;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International
Conference_Location
Cambridge, MA
Print_ISBN
978-0-7695-4979-8
Type
conf
DOI
10.1109/IPDPSW.2013.116
Filename
6651081
Link To Document