A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM

Author

Schepis, D.J. ; Assaderaghi, F. ; Yee, D.S. ; Rausch, W. ; Bolam, R.J. ; Ajmera, A.C. ; Leobandung, E. ; Kulkarni, S.B. ; Flaker, R. ; Sadana, D. ; Hovel, H.J. ; Kebede, T. ; Schiller, C. ; Wu, S. ; Wagner, L.F. ; Saccamango, M.J. ; Ratanaphanyarat, S. ;

Author_Institution

Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

587

Lastpage

590

Abstract

In this paper a 0.25 /spl mu/m SOI CMOS technology is described. It uses undepleted SOI devices with nominal channel length of 0.15 /spl mu/m, minimum channel length in the 0.1 /spl mu/m range, supply voltage of 1.8 V, local interconnect, 6 levels of metal, and same ground rules as the comparable bulk 0.25 /spl mu/m CMOS. Key technology elements considered include device, performance, reliability, ESD, and circuit functionality. Using this SOI CMOS, a 4 Mb SRAM is demonstrated. This is the highest performance 0.25 /spl mu/m CMOS technology reported to date.

Keywords

CMOS digital integrated circuits; CMOS integrated circuits; CMOS memory circuits; SRAM chips; electrostatic discharge5802284; integrated circuit reliability; integrated circuit technology; microprocessor chips; silicon-on-insulator; 0.25 micron; 1.8 V; 4 Mbit; CMOS SOI technology; CMOS SRAM; ESD; Si; circuit functionality; local interconnect; reliability; static RAM; submicron process; undepleted SOI devices; Breakdown voltage; CMOS technology; Electrostatic discharge; Heating; Integrated circuit interconnections; Isolation technology; Microelectronics; Random access memory; Research and development; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650453

Filename

650453