DocumentCode :
1999655
Title :
An improved feedthrough logic for low power circuit design
Author :
Sahoo, Sauvagya Ranjan ; Mahapatra, Kamala Kanta
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India
fYear :
2012
fDate :
15-17 March 2012
Firstpage :
713
Lastpage :
716
Abstract :
This paper presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The proposed circuit has very low dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The concept is validated through extensive simulation. The problem of requirement of output inverter and non-inverting logic are also completely eliminated in the proposed design.
Keywords :
CMOS logic circuits; invertors; CMOS domino logic family; feedthrough logic improvement; inverter; low power circuit design; transistor requirement; Adders; CMOS integrated circuits; Inverters; Power demand; Power dissipation; Simulation; Transistors; Feedthrough logic (FTL); dynamic CMOS logic circuit; low-power adder;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Recent Advances in Information Technology (RAIT), 2012 1st International Conference on
Conference_Location :
Dhanbad
Print_ISBN :
978-1-4577-0694-3
Type :
conf
DOI :
10.1109/RAIT.2012.6194582
Filename :
6194582
Link To Document :
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