Gate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiO/sub x/ interlayer for reliability in sub-micrometer CMOS

Author

Ito, H. ; Sasaki, Motoharu ; Kimizuka, N. ; Uwasawa, K. ; Ito, Takao ; Goto, Yasunori ; Tsuboi, A. ; Watanuki, S. ; Ueda, Toshitsugu ; Horiuchi, T.K.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

635

Lastpage

638

Abstract

The proposed gate electrode structure consists of two stacked large-grain poly-Si layers with an ultra-thin SiO/sub x/ interlayer. A CMOS with this gate has two advantages: (I) three times larger Q/sub BD/ and a more than ten-fold improvement for V/sub TH/ shift in the BT test at 250/spl deg/C, indicating high tolerance against slow trap generation compared with an as-deposited poly-Si gate, and (II) less than 10% gate depletion for both nMOS and pMOS without boron penetration in pMOS. The fabrication of this structure is very compatible with the dual-gate CMOS process.

Keywords

CMOS integrated circuits; MOSFET; VLSI; electron traps5802295; elemental semiconductors; grain size; impedance matching; integrated circuit measurement; integrated circuit reliability; mixed analogue-digital integrated circuits; silicon; 250 degC; Si-SiO; dual-gate CMOS process; gate depletion; gate electrode microstructure; reliability; slow trap generation; stacked large-grain polysilicon; sub-micrometer CMOS; threshold voltage shift; Boron; CMOS process; Electrodes; Fabrication; Grain size; Indium tin oxide; MOS devices; MOSFETs; Microstructure; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650464

Filename

650464