Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetration

Author

Tseng, H.-H. ; Tsui, P.G.Y. ; Tobin, P.J. ; Mogab, J. ; Khare, M. ; Wang, X.W. ; Ma, T.P. ; Hegde, R. ; Hobbs, C. ; Veteran, J. ; Hartig, M. ; Kenig, G. ; Wang, V. ; Blumenthal, R. ; Cotton, R. ; Kaushik, V. ; Tamagawa, T. ; Halpern, B.L. ; Cui, G.J. ; Sc

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

647

Lastpage

650

Abstract

The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when Jet Vapor Deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface and well behaved bulk properties, MOSFET characteristics, and ring oscillator performance. Process optimization and manufacturing issues remain to be addressed.

Keywords

dielectric thin films; 0.35 micron; CMOS process; JVD nitride gate dielectric; MOSFET characteristics; Si-Si/sub 3/N/sub 4/-Si; boron penetration; bulk properties; gate leakage current; jet vapor deposition; ring oscillator performance; scaled gate dielectrics; Boron; CMOS process; CMOS technology; Chemical vapor deposition; Dielectric devices; Leakage current; MOSFET circuits; Manufacturing processes; Ring oscillators; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650467

Filename

650467