A technique for power reduction of CMOS circuit at 65nm technology

The overall power consumption in nano-scaled device has reached an alarming state mainly due to the increasing trend of various leakage components. This escalated power consumption leads to device characteristics breakdown due to hot-spot creation within the integrated Package. As a result, as technology advances overall power dissipation of VLSI circuit needs to be controlled by power-aware design. Here we propose an idea through which we can reduce the overall power consumption by simple modification in the reference circuit. Pre-layout and post-layout simulation of modified circuit shows a significant improvement in power consumption. Power saving has been compared with the existing leakage reduction technique such as transistor stacking. The area and delay overhead for the implementation of the modified structure are very less.