A read-monitored write circuit for 1T1M multi-level memristor memories

Technology migration into nano and molecular scales has led to the design of several hybrid CMOS/nano logic and memory architectures that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale memory and logic systems by facilitating the implementation of multi-level logic. In this work we propose a sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit storage in each data cell (memristor). Robust read and write methodologies for the proposed architecture are also discussed and tradeoffs between faster write speeds and larger read noise margins are also analyzed. Another highlight of this work is the usage of the exponential drift memristor model to further enhance write speeds of these devices which are otherwise much slower.