CMOS interface circuits for reading and writing memristor crossbar array

This paper describes CMOS interface circuits in 350nm 3.3V/5.0V TSMC process for memristor crossbar array. These circuits are applicable for non-volatile resistive memories. The architecture is targeted for low power and high speed applications. We have demonstrated sense amplifiers for reading the state of a memristor bit. Voltage divider and transimpedence amplifier is used for DC sensing while sigma delta approach is used for averaging. Current limiting write amplifier has also been designed for increasing the device endurance and reliability. Half select array architecture is used to minimize dc leakage current in the crossbar array.