Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs

Contrary to the bounded clock skew scheduling, which controls the clock signal arrival times of flip-flops (FFs) so that all clock skews are within a given bound, the useful clock skew scheduling exploits the time borrowing between signal paths by controlling the clock times in a way to meet the timing constraints of the individual signal paths, thus enabling a further improvement of clock frequency. However, even though there are many works on the useful clock skew scheduling, most of them are targeted to designs with single power mode. This work addresses the problem of useful clock skew scheduling for designs with multiple power modes, which is nowadays an essential concept for low-power designs. Precisely, we propose an optimal solution of the problem of useful clock skew scheduling for designs of multiple power modes with the objective of minimizing the number of adjustable delay buffers (ADBs) used. In addition, we solve two practical extensions: optimally allocating ADBs having quantized delay values and optimally allocating ADBs with delay upper bound. The experiments with benchmark circuits show that our proposed algorithm reduces the number of ADBs by 14.0% on average over the results produced by the conventional ADB allocation of useful clock skew scheduling for designs with multiple power modes, and reduces the number of ADBs by 77.3% on average over that produced by the previous optimal ADB allocation of bounded clock skew scheduling for designs with multiple power modes.