DocumentCode
2000015
Title
Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture
Author
Chang, Jed Kao-Tung ; Chen Liu ; Gaudiot, Jeen-Luc
Author_Institution
Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
fYear
2013
fDate
20-24 May 2013
Firstpage
2035
Lastpage
2044
Abstract
Data encryption/decryption has become an essential part of modern information systems. However, executing these cryptography algorithms introduces high overhead issues for performance, power, and hardware cost. Through profiling work, we found that cryptography algorithms are data-intensive, and memory access overhead plays an important role in downgrading the performance. We found that the instructions in Load-Store Block (LSB) patterns account for more than 30% of total instruction count for certain algorithms. Based on this, we propose a Processor-in-Memory (PIM) architecture to efficiently execute the application by reducing the memory access penalty caused by a large amount of memory accesses. We divided the memory module into segments and implemented the Load-Store Block of the chosen algorithm as the processing element in the PIM module. By having each of these segments run concurrently, our implementation achieves speedups as high as 200 to 500 folds for various sizes of LSB and around 1.5 folds for the overall algorithm when the number of modules is eight. Overall, by implementing the LSB into the memory module on our proposed architecture, the performance of the cryptography application can be enhanced significantly, with superb energy efficiency and marginal hardware cost.
Keywords
cryptography; random-access storage; PIM architecture; cryptography algorithms; data decryption; data encryption; load-store block patterns; marginal hardware cost; modern information systems; processor-in-memory architecture; superb energy efficiency; Algorithm design and analysis; Benchmark testing; Computer architecture; Encryption; Hardware; Cryptography; Load-Store Block (LSB); Performance Analysis; Processor-in-Memory Architecture (PIM);
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International
Conference_Location
Cambridge, MA
Print_ISBN
978-0-7695-4979-8
Type
conf
DOI
10.1109/IPDPSW.2013.187
Filename
6651108
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