Performance of front-end readout system for PHENIX RICH

Author

Oyama, K. ; Hamagaki, H. ; Nishimura, S. ; Shigaki, K. ; Hayano, R.S. ; Hibino, M. ; Kametani, S. ; Kikuchi, J. ; Matsumoto, T. ; Sakaguchi, T. ; Ebisu, K. ; Hara, H. ; Tanaka, Y. ; Ushiroda, T. ; Moscone, C.G. ; Wintenberg, A.L. ; Young, G.R.

Author_Institution

Center for Nucl. Study, Tokyo Univ., Japan

fYear

1999

fDate

1999

Firstpage

427

Lastpage

432

Abstract

A front-end electronics system have been developed for the ring imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA´s and CPLD´s were developed for high performance real time data acquisition. The transfer rate of the back-plane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 μs per event. The design specifications and test results of the system are presented in this paper

Keywords

Cherenkov counters; analogue integrated circuits; application specific integrated circuits; data acquisition; field programmable gate arrays; nuclear electronics; 640 MB/s; CPLD; FPGA; PHENIX experiment; RICH; custom analog ASIC; front-end electronics; high speed custom back-plane; real time data acquisition; ring imaging Cerenkov detector; transfer rate; Application specific integrated circuits; Charge measurement; Current measurement; Detectors; Electrons; Laboratories; Nuclear electronics; Plasma accelerators; Plasma properties; Pulse measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

Real Time Conference, 1999. Santa Fe 1999. 11th IEEE NPSS

Conference_Location

Sante Fe, NM

Print_ISBN

0-7803-5463-X

Type

conf

DOI

10.1109/RTCON.1999.842660

Filename

842660