DocumentCode :
2001128
Title :
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement
Author :
Fujimoto, Daisuke ; Nagata, Makoto ; Bhasin, Shivam ; Danger, Jean-Luc
Author_Institution :
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
fYear :
2015
fDate :
19-22 Jan. 2015
Firstpage :
749
Lastpage :
754
Abstract :
For security-critical applications, the security and trust of devices must be tested before shipping. In this paper, we promote the use of On-Chip Power noise Measurements (OCM), in order to test security using side-channel techniques. We then propose for the first time a standard side-channel measurement setup using OCM. Finally, we provide some key ideas on methodology to integrate the validation of hardware security and trust in the standard testing flow, exploiting OCM.
Keywords :
integrated circuit testing; noise measurement; system-on-chip; OCM; hardware security; on-chip power noise measurement; security-critical applications; shipping; side channel measurement setup; side channel techniques; test security; Hardware; Noise; Noise measurement; Semiconductor device measurement; Testing; Trojan horses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
Type :
conf
DOI :
10.1109/ASPDAC.2015.7059100
Filename :
7059100
Link To Document :
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