DocumentCode
2001480
Title
A new topology for parallel resonant DC link with reduced peak voltage
Author
Deshpande, V.V. ; Doradla, S.R.
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
fYear
1994
fDate
13-17 Feb 1994
Firstpage
260
Abstract
A new topology for a parallel resonant DC link is proposed. It offers reduced peak DC link voltage without generating high di/dt. The effect of various parameters on the link voltage waveform is discussed. A design procedure is outlined to determine the component values for any desired resonant frequency. A comparison with the actively clamped circuit is given. There is an excellent correlation between the experimental and simulation results
Keywords
circuit resonance; invertors; power convertors; actively clamped circuit; design procedure; inverters; link voltage waveform; parallel resonant DC link; peak voltage reduction; topology; Clamps; Frequency; Inductors; RLC circuits; Radiofrequency interference; Resonance; Stress; Topology; Virtual colonoscopy; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 1994. APEC '94. Conference Proceedings 1994., Ninth Annual
Conference_Location
Orlando, FL
Print_ISBN
0-7803-1456-5
Type
conf
DOI
10.1109/APEC.1994.316390
Filename
316390
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