A New Methodology for the Test of SoCs and for Analyzing Elusive Failures

The increasing complexity of SoCs in form of more complex architecture designs and smaller structures qualifies test procedures and failure analysis as one of the key skills in the semiconductor industry. In this contribution we show a new SoC test methodology which significantly increases the test coverage of a SoC. The integrated system integrity control functionality of the hid ICE approach observes a SoC core and is able to detect irregularities in comparison to a reference system. In case of a failure detection an exhaustive trace is available which helps to identify the root cause. Especially in multi-core systems the interference between different subsystems can be tested under real operating conditions. Also the effort to identify and analyze elusive failures will be reduced.